A digital system, such as an embedded system, typically contains multiple integrated circuit (“IC”) devices. A number of standard interfaces have been established for the various IC devices to communicate with each other or with outside devices. Typically, control, diagnostic and power management information as well as data are exchanged via an interconnecting serial bus according to specified protocols and electrical signals.
For example, one industry standard serial bus is the I2C-bus defined by Phillips Semiconductors, Eindhoven, The Netherlands (www.semiconductors.philips.com/buses/i2c/.) Another standard serial bus interface compatible with the I2C bus is the System Management (“SM”) bus defined by Intel® Corporation, California, U.S.A (www.smbus.org.) These and other serial bus interfaces allow IC devices to exchange control signals, addresses and data serially among themselves or with the outside world with a minimum of wires.
FIG. 1A illustrates a typical communication system in which various IC devices are interconnected by a serial bus. The system 10 contains a number of devices such as devices 20, 30-1, 30-2, . . . , 30-n. Typically one of the devices in the system initiates a communication link with another device on the bus 100. The initiating device assumes the role of a master device, such as device 20, and the device being called on assumes the role of a slave device, such as device 30-1.
FIG. 1B illustrates a specific example of a serial bus shown in FIG. 1A as being a bi-directional, 2-wire bus. The 2-wire serial bus 100 is constituted with a data wire 102 for carrying data and a clock wire 104 for carrying clock signals.
FIG. 2 illustrates an example bus protocol between a master device reading data from a slave device. The data in the slave device typically reside in a memory accessible via an internal bus of the slave device.
Each slave device on the bus is usually listening to any messages broadcast by a master device onto the serial bus 100. In bus transaction #1, the master device 20 attempts to communicate with a targeted slave device, such as 30-1, by putting out the targeted slave address onto the serial bus 100. It issues a message containing control signals and address, such as a START signal followed by a SLAVE ADDRESS word, followed by a read or write (R/W) control bit.
Each slave will be activated by a bus activity such as the arrival of the START signal from the master device. Upon activation each slave immediately sets out to perform two tasks. One is to start reserving its internal bus for possible memory access by the master device. The other task is to shift in the ADDRESS word and determine if it is the targeted slave device.
In bus transaction #2, each slave device will shift in the R/W control bit and the slave address. Only the targeted slave device (e.g., the slave device 30-1) with the matching address will reply and establish communication with the calling master device by returning an acknowledgement, ACK, signal. The other slave devices not matching the slave address do not respond.
In bus transaction #3, when the master device 20 is so acknowledged by the matching slave device, it transmits a train of clock signals to latch a block of data from the targeted slave device 30-1 through the bus 100. Upon successful completion of the transfer of one block of data, the master device issues an ACK signal followed by the next clock train to transfer the next block of data from the targeted slave device. In bus transaction #4, the data reading process continues until the master device signifies an end to the data transfer by issuing a STOP signal to the targeted slave device.
As mentioned earlier, each slave device needs to reserve its internal bus and memory resource as soon as a bus activity is detected (bus transaction #1.) This is necessary for each slave device while address identification is going on in order to allow sufficient time to get its memory ready for access in the short time leading to transaction #3, should the slave turn out to be the targeted one. In other words, owing to the timing requirement of the serial bus protocol, the serial bus access has a limited latency. When a master device is accessing the memory of a slave device via the serial bus, its access must be completed within the latency limit, otherwise serious error will occur. To support this, each slave device will typically begin to reserve memory resource ownership as soon as bus activity is detected.
Thus, until the address identification process is completed (end of bus transaction #2), all slave devices on the serial bus basically have their internal bus or memory resource reserved for external access to the exclusion of their internal agents. While this works fine when the bus access is destined for the memory resource, it may very well be that the access is intended for another slave device entirely, or for a separate function on the same device. This means all the non-targeted slave devices on the serial bus will have their internal bus or memory resource tied up for no purpose; and they will not find out until the slave address has been shifted in, compared and determined to be a mismatch. During that period, the memory resource of each slave device is unavailable to any of its internal agents.